TTL (transistor-transistor logic) signaling is commonly used to communicate data between devices present on a printed circuit board (PCB). For example, a field programmable gate array (FPGA) present on a PCB may use TTL signaling to communicate data to another device present on the PCB. Those skilled in the art will appreciate that TTL signaling has traditionally provided a reliable mechanism for communicating digital data between devices. However, as data transfer requirements continue to increase, limitations associated with TTL signaling become more problematic.
Because rather large amplitude signals are used in TTL signaling, it takes a relatively long time to swing between rail voltages. Also, a high capacitance associated with TTL signals, when combined with a bus structure, causes edges of the TTL signals to be attenuated. Consequently, a maximum frequency of TTL signals traveling through a PCB is limited to less than 200 MHz. Additionally, TTL signals tend to consume large amounts of power at higher frequencies due to the wide signal swing and high capacitance. Therefore, in applications requiring higher bandwidth/higher speed data transmission, the TTL signaling approach can be less than optimal.
When higher bandwidth/higher speed data transmission is needed, a LVDS (low voltage differential signaling) method can be used instead of the TTL signaling method. As those skilled in the art will appreciate, relative to the TTL signaling method, the LVDS method provides faster bit rates, lower power consumption, and better noise performance. Because data transmitted using the LVDS method is represented by a differential voltage between two transmission lines carrying equal and opposite currents, the transmitted data represented by the differential voltage is immune to common-mode noise. Additionally, LVDS lowers voltage swings to about 300 mV. Thus, LVDS differential signals can change state very fast. Furthermore, the low voltage swing of LVDS provides reduced power consumption.
Even though LVDS has certain advantages over TTL signaling, both LVDS and TTL signaling continue to be used for data communication, depending on the particular application. When designing an FPGA to be used in a wide variety of applications, it is necessary to provide both TTL signaling and LVDS capability. Thus, the available FPGA output buffers need to provide a sufficient number of single-ended TTL drivers for TTL signaling and a sufficient number of differential drivers for LVDS. Consequently, to support the wide variety of potential applications, the cost of the FPGA includes the cost of both the TTL drivers and the differential drivers. For FPGA end-users that do not require the full LVDS capability of the FPGA, the included cost of the unused differential drivers is wasted. Similarly, for FPGA end-users that do not require the full TTL signaling capability of the FPGA, the included cost of the unused TTL drivers is wasted.
In view of the foregoing, a solution is needed for providing an FPGA that includes both TTL signaling capability and LVDS capability in a more economical manner.